MediaTek Inc.

Design Verification Engineer

Singapore

Bachelor’s degree in Electrical Engineering, Computer Engineering or related

Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan.

Analog RF Design Engineer

Singapore

Bachelor's Degree Master’s Degree in EEE (major in IC Design)

• Design of RF/Analog/Mixed-signal IC circuit blocks/ IPs based on specifications (performance,area,powerconsumption).
• Realize IC layout with floor planning and performan ceconsiderations (withlayoutengineers).
• Testing & Debugging of IC prototypes (withsystemverificationengineers).
• Support of IC tomass production ready.
• Continual support / debug of field related issues or customer IC rejects.
• IC design and performance documentation.

SOC Digital Design Engineer

Singapore

Bachelor’s degree in Electrical Engineering, Computer Engineering or related

• Develops the logic design, RTL coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Follows secure development practices to address the security threat model and security objects within the design.
• Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IP to SoC hand off.

Physical Verification Sign-off Engineer

Singapore

Pursuing a degree in Electrical/Electronics/Computer Science Engineering

You will be involved in:

• Execute design rule checks on real chip design
• Debug real issues related to design rule checks happening at full chip integration
• Do basic reporting on physical verification issues
• Basic project management/project risk assessment reporting
• Basic scripting automation

Software Engineer (Physical Verification)

Singaproe

pursuing a degree in Computer, Software or Engineering related studies

• Involve in various stages of the software development lifecycle, including requirements gathering, design and
• implementation, and deployment.
• Develop, improve and maintain CAD flow & methodology for ensuring correct electrical and logical functionality and manufacturability.
• Work closely with team members and develop solutions using Open-Source Software technology.
• Directly involved in our physical verification methodology efforts, collaborating right alongside our internal multi- functional teams to ensure that our products achieve best-in-class PPA (Power, Performance & Area) and time-to- market.

Full Custom Layout Engineer

Singapore

Bachelor’s degree in Electrical/Electronic Engineering

• Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones
• Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
• Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule
• Responsible for in-house IP/library developments

IC Physical Design Engineer

Singapore

Basic knowledge of electronic design or IC design, internship experience in related area is preferred

• IC physical design of 12nm/6nm/4nm and below world leading advanced process chip, from RTL to GDS.
• Block owner, take block of 2~3 Million instances, working on Synthesis/APR(auto place and route)/Signoff
• Block coordinator role for more than 5~10 blocks, solving the critical issue and give the solution to block owners.
• TOP role for the complicated hierarchical chip (more than 20 Million instances plus 500+ macros), doing floorplan and partition, responsible for full chip tape out

Memory Design Automation Engineer

Singapore

Bachelor/Master Degree in Electrical and Electronic Engineering/Computer Engineering/Computer Science

• Own cutting edge technology node’s SRAM compiler design and deliver best quality of design kit
• Seamlessly collaborate with SRAM design team to achieve highest quality of design kit delivery
• Responsible for data analysis and platform development of memory usage big data
• Responsible for physical verification (DRC/ERC/LVS/ANT) on SRAM compiler
• Responsible for spice simulation on timing, power and noise on SRAM compiler
• Responsible for QA check and development on SRAM compiler

Standard Cell Library Characterization Engineer

Singpore

Engineering/Computer Engineering/Computer Science, no prior experience is required

• Responsible for Standard Cell Library Characterization for leading edge process node (7nm/5nm/4nm/3nm), as
• the pioneer to setup design platform for MediaTek projects.
• Perform timing/power/constraint/noise modeling for >15K logic circuit for one process node.
• Perform LVF modeling, statistical variation simulation and analysis
• Co-work with designer and tool vendors to tackle modelling difficulties, and solve the accuracy and runtime issues, especially for customized circuit cannot be handled by commercial tools.
• Responsible for flow development, new kits enablement and evaluation, e.g., EM characterization, Aging characterization.
• Data trend analysis in machine learning for circuit performance and power assessment.
• Involve in sub-threshold voltage circuit characterization and verify functionality with expected PPA

Timing Signoff Engineer

Singapore

Bachelor’s/Master’s Degree in Electrical/Computer Engineering

• Work on timing sign off, convergence, automations and methodology development.
• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Experience in design automation using TCL/Perl/Python
• Familiar with process technology enablement: Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
• Strong expertise in STA timing analysis basics, AOCV/POCV/LVF concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

GPU/APU Physical Implementation Engineer

Singapore

Bachelor’s/Master’s Degree in Electrical/Computer Engineering

• Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DSP
• Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP
• Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization
• Implementation flow development
• Work closely with MediaTek’s colleagues in Taiwan and Singapore in implementation methodology co-development and flow deployment